The SPARC chip family includes several successive levels (or other variants) of chip, using the same core instruction set, but including a few additional instructions at each level.
By default, as
assumes the core instruction set (SPARC
v6), but "bumps" the architecture level as needed: it switches to
successively higher architectures as it encounters instructions that
only exist in the higher levels.
-Av6 | -Av7 | -Av8 | -Av9 | -Asparclite
as
reports a fatal error if it encounters an instruction
or feature requiring a higher level.
-bump